1. Field of the Invention
The present invention relates generally to implementing array antenna and radar systems, and more particularly to implementing true time delay digital beamformers.
2. Related Art
Phased array antennas, such as are commonly used in radar, consist of multiple stationary antenna elements, which are fed coherently and use variable phase or time-delay control at each element to scan a beam to given angles in space. The primary reason for using phased arrays is to produce a directive beam that can be repositioned (scanned) electronically. True time delays are required when the difference in arrival times of signals across the array is greater than the reciprocal of the signal bandwidth. Since the difference in arrival times is a function of the angle of arrival, the need for true time delays is based on the maximum scan angle. A reference in this field is authored by Robert J. Maillous, entitled xe2x80x9cPhased Array Antenna Handbookxe2x80x9d, published by Artech House, 1994.
One conventional method for achieving the time delays required is by using transmission line based delay media. According to one approach, each signal is switched to one of a plurality of radio frequency (RF) cables or optical fiber cables, each having a different length. By routing a signal through a cable of a particular length, a known delay can be imposed upon the signal.
One disadvantage of this approach is that the lengths of the cables must be controlled precisely to achieve the precise delays required by beamforming. In addition, the cables corresponding to specified delays must be RF phase matched relative to reference cables. This matching process is costly and time-consuming.
Another disadvantage to this approach is that the switches and cables are lossy. As the RF signals pass through various circuits, switches, cables, and the like, amplifiers are required to keep the signals above the noise level. These amplifiers add cost, size and weight and require additional power.
Another conventional method for implementing the true time delays is to use a digital signal processor (DSP). According to this method, analog-to-digital converters (A/D) are used to convert the signals to be delayed into digital form. The resulting digital signals are then processed by the DSP to achieve the desired signal delays.
The DSP approach has three significant disadvantages when the clocking frequencies are greater than, say, one GHz. First, GHz digital signals contain high frequency harmonics, thus controlled impedance transmission lines or 50 ohm lines are required to implement the interconnections between DSP modules. For example, a 2 GHz clock signal contains a harmonic at 6 GHz with a significant amplitude of about 30% of the amplitude of the fundamental harmonic. Since the wavelength at 6 GHz is about 1.1 inch for a low dielectric permittivity material (that is, a low-K material), to preserve the shape and integrity of GHz digital signals, reflections of harmonics must be minimized. Interconnecting GHz digital signals between DSP modules is a time consuming and costly task that requires the application of microwave engineering, involving design, simulation, testing, and verification.
Second, the DSP would have numerous inputs and outputs. This results in numerous interconnections, each of which requires power to drive. This is especially the case when the speed of the digital data is on the order of 1 GHz or more, because each interconnect is terminated into, say, a 50 ohm load that requires power to drive.
Third, the distribution of high frequency data and clock signals requires higher quality and more expensive transmission lines. An analog signal conveying the same amount of information as the digital signals requires less bandwidth. Thus analog signals could be distributed on lower quality and less expensive transmission lines.
Finally, the distribution and summation of digital signal require more power because the voltage levels required by digital logic circuits are relatively high. On the other hand, the distribution and summation of analog signal require less power, because these functions can be accomplished at relatively low voltage levels.
The present invention is an apparatus for the implementation of a true time delay digital beamformer. An architecture is disclosed for the hardware implementation of true time delay digital beamformers, for forming transmit as well as receive beams in array antennas. The present invention provides the logic circuit design for the hardware implementation of mixed signal application-specific integrated circuits (ASIC). Also disclosed is the logic circuit design for the hardware implementation of the circuit, comprising a collection of hard-wired finite impulse response (FIR) filters that provide programmable fractional delays.
The present invention is an apparatus for use in a mixed signal true time delay digital beamformer. The apparatus includes a mixed signal application-specific integrated circuit (ASIC) having an analog-to-digital converter (A/D), a digital delay unit coupled to the A/D output, and a digital-to-analog converter (D/A) coupled to the digital delay unit output.
According to one embodiment, the apparatus includes a further mixed signal ASIC and an analog combiner coupled to the D/A output of each mixed signal ASIC.
In one aspect, the apparatus includes a low pass filter coupled to the output of the analog combiner; a gain control element coupled to the output of the low pass filter; and a further A/D coupled to the output of the gain control element.
In one aspect, the apparatus includes first and second subarrays that receives an electromagnetic signal; first and second downconverters respectively coupled to the first and second subarrays; and first and second low pass filters respectively coupled to the first and second downconverters; wherein the first and second low pass filters are respectively coupled to the mixed signal ASIC and the further mixed signal ASIC.
According to another embodiment, the apparatus includes a further mixed signal ASIC; and a splitter coupled to the input of each mixed signal ASIC.
In one aspect, the apparatus includes a gain control element coupled to the to the input of the splitter; a low pass filter coupled to the to the input of the gain control element; and a further D/A coupled to the input of the low pass filter.
In one aspect, the apparatus includes first and second low pass filters respectively coupled to the mixed signal ASIC and the further mixed signal ASIC; first and second upconverters respectively coupled to the first and second low pass filters; an upconverter coupled to the output of the D/A; and first and second subarrays respectively coupled to the first and second upconverters.
In one aspect, the digital delay unit includes a shift register as an input circuit; a multiplexer coupled to the shift register outputs; and a digital filter coupled to the multiplexer outputs.
In one aspect, the digital filter includes a plurality of finite impulse response (FIR) filters, wherein each FIR filter is activated and selected as the output of the digital filter according to a filter select signal.
In one aspect, the apparatus each FIR filter is hard-wired to implement a unique predetermined time delay.
One advantage of the present invention is that it represents a significant reduction in size, weight, power, and interconnect complexity when compared to a digital beamformer based on a conventional design.
Another advantage of the present invention is that it minimizes interconnections, by a factor of four or more.
Further features and advantages of the present invention as well as the architecture and the operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings.